The present invention generally relates to semiconductor integrated circuits, and more particularly to a compound semiconductor integrated circuit for producing a relatively large output voltage.
Generally, a thin active layer is used to reduce the pinch-off voltage of the field effect transistor (FET). However, when a compound semiconductor material such as GaAs is used and a surface depletion layer is introduced due to the surface levels, the surface depletion layer occupies an increasing amount, or proportion, of increases the channel increases and the channel becomes correspondingly narrower. As a result, the stray resistance, particularly the source resistance R.sub.s increases, thereby reducing the mutual conductance. Accordingly, various measures are taken to reduce the effects of the surface depletion layer in order to minimize the stray resistance.
One such measure involves the so-called self-aligned type FET. The self-aligned type FET has an impurity layer of high impurity concentration formed in self-alignment with the gate electrode. The stray resistance R.sub.s can be made extremely small because the impurity layer reaches the vicinity of the gate.
FIG. 1 shows an example of a conventional semiconductor integrated circuit. In FIG. 1, a logic part 10 forms an internal circuit, and a driver part 11 drives a load. The logic part 10 converts an internal signal S.sub.1 into a logic signal S.sub.2 and an inverted signal S.sub.2X of the logic signal S.sub.2. The driver part 11 amplifies the logic signals S.sub.2 and S.sub.2X into driving signals S.sub.3 and S.sub.3X which are sufficiently large to drive the load. The logic part 10 includes a self-aligned type FET T.sub.1. On the other hand, the driver part 11 includes self-aligned type FETs T.sub.2 through T.sub.4 and resistors R.sub.1 and R.sub.2 which are connected as shown.
The amplitudes of the driving signals S.sub.3 and S.sub.3X are determined by terminal voltages E.sub.R1 and E.sub.R2 developed across the respective resistors R.sub.1 and R.sub.2 in relation to the switching operation of the respectively associated FETs T.sub.2 and T.sub.3. For example, the amplitude of the driving signal S.sub.3 is obtained by subtracting the drain voltage V.sub.D2ON (=V.sub.DD -E.sub.R1) of the FET T.sub.2 when it is ON from the drain voltage V.sub.D2OFF (=V.sub.DD) of the FET T.sub.2 when it is OFF, that is, the amplitude of the driving signal S.sub.3 is given by E.sub.R1.
However, since the FETs T.sub.2 through T.sub.4 used in the driver part 11 of the conventional semiconductor integrated circuit are of the self-aligned type, the amplitude of the driving signals S.sub.3 and S.sub.3X is only 5 V at the maximum, and only 3 V if safety factor is taken into consideration. For this reason, there is a problem in that the conventional semiconductor integrated circuit cannot be used to drive a load which requires a driving signal which is greater than 5 V.
In other words, in order to make the amplitude of the driving signals S.sub.3 and S.sub.3X greater than 5 V in FIG. 1, it is necessary to set the potential difference of the two power source voltages V.sub.DD and V.sub.SS to at least 10 V or greater. But if the potential difference of the two power source voltages V.sub.DD and V.sub.SS is set to 10 V or greater, this potential difference of 10 V or greater is applied across the drain and source of the FET T.sub.2 (or T.sub.3) which is OFF. Since the drain withstand voltage of the self-aligned type FET is in the range of 4 V to 6 V at the most, the FET T.sub.2 (or T.sub.3) breaks down permanently in this case.
It is conceivable to use non-self-aligned FETs in the driver part 11 in order to obtain a drain withstand voltage higher than that obtainable by the self-aligned type FETs T.sub.2 through T.sub.4. However, in the case of the self-aligned type FET and the non-self-aligned type FET having the same gate electrode length, the gap between the two impurity regions is much smaller for the self-aligned type FET. For this reason, if the driver part 11 uses the non-self-aligned type FETs having the same gap between the two impurity regions as the self-aligned type FETs T.sub.2 through T.sub.4 in order to obtain the same performance, the gate electrode length of each non-self-aligned type FET must be made extremely small. However, the gate electrode length of each of the self-aligned type FETs T.sub.2 through T.sub.4 is relatively small to start with, when the driver part 11 is formed as an integrated circuit having a satisfactorily high integration density; thus, and it is extremely difficult to further reduce the electrode length of the non-self-aligned type FET compared to the corresponding gate electrode length of the self-aligned type FET. On the other hand, the gate electrode length of the non-self-aligned type FET must be increased to increase the gap between the two impurity regions in order to improve the drain withstand voltage, but this contradicts to the need to decrease the gap in order to obtain the same performance as the self-aligned type FET. Therefore, the above described problem cannot be eliminated by merely using non-self-aligned type FETs in the driver part 11.